SDR SDRAM PCB Timing Budget
I am working on routing a microprocessor to two identical single data rate (SDR) SDRAM chips that are PC166 compliant, particularly Alliance AS4C16M16SB-6TIN. The 16 bit SDRAM chips are combined to form a 32 bit word. The microprocessor is of the NXP i.MX RT1170 family and has an external memory controller that supports PC166. How can one use the data sheets for both parts to determine PCB routing requirements such as length matching between particular nets and the maximum length any net can be? In other words how do you use the data sheets to determine a timing budget for the PCB interconnect?
Based on Olin's great response I added the links for the data sheets (above) and below I attempt at determining the timing requirements. I would appreciate any feedback on the analysis.
Processor Output, Memory Input Direction:
Page 21 of the memory data sheet states that the chip has a minimum Data/Address/Control Input set-up time of 1.5ns, and a minimum Data/Address/Control Input hold time of 0.8ns. Thus the data, address, and control signals need to be at the chips pin for at least 2.3ns.
Page 62 of the processor data sheet states that the chip has a maximum Data Output Valid time of 0.6ns and a minimum data output hold time of -0.7ns. So if I understand correctly, assuming a 167MHz clock, which is a period of 5.99ns, the valid data arrives at 5.99ns/2 - 0.6ns = 2.40ns before the positive clock edge and remains valid for 5.99ns/2 + -0.7ns = 2.30ns after the positive clock edge. Thus the output window is 2.40ns + 2.30ns = 4.70ns.
Luckily the processor output window exceeds the minimum memory input window. Further, the clock does not need to be skewed because the memory input setup and hold times are met individually too. The margin for the setup time is 2.40ns - 1.5ns = 0.9ns. The margin for the hold time is 2.3ns - 0.8ns = 1.5ns.
Processor Input, Memory Output Direction: Page 64 of the processor data sheet states that the chip has a minimum data input setup of 0.6ns, and a minimum data input hold of 1ns. Thus the total window required is 0.6ns + 1ns = 1.6ns.
Page 21 of the memory data sheet states that the chip has a minimum access time from positive clock edge of 6ns or 5ns for a CAS latency setting of 2 or 3 clock cycles respectively. The chips has a minimum data output hold time of 2.5ns. Assuming a 167MHz clock again (5.99ns period), the data output from the memory chip is 0.01ns after the positive clock edge, or 0.99ns before the positive clock edge (where the clock edge is the clock that the memory chip sees). The total output window is either -0.01ns + 2.5ns = 2.49ns or 0.99ns + 2.5ns + 3.49ns for the CAS latency of 2 and 3 respectively.
Thus both options meet the total window required by the processor. However, assuming there was no propagation delay between the processor and memory, only the latter case (CAS latency of 3) meets the setup time requirement in addition to the hold requirement. The margin for the case of CAS latency of 3 is 0.99ns - 0.6ns = 0.33ns for the setup time, and 2.5ns - 1ns = 1.5ns for the hold time.
Accounting for Propogation Delay: The previous analysis showed that the smallest margin of both directions of operation is 0.33ns, which is the case for when the processor is reading from memory. Assuming the propogation speed on the PCB is 6in/ns, then the trace lengths between the processor and the memory chip need to be less than (0.33ns/2)*(6in/ns) = 0.99 in. This maximum distance does not seem feasible (the SDRAM chip package is large). So I think that if I want to use this memory chip, I will need to run it at a slower clock, perhaps 143MHz.
Is the above analysis valid?
1 answer
It would help to provide links in your question to the datasheets.
Without the datasheets I can only give general advice. Look a the memory datasheet and see what the setup and hold time requirements are. There is always a window of time around a clock edge where the data must be held steady on a write. This is the window that you have to guarantee will always be met at the chip pins.
Look at the reverse specifications for reading from the memory. Now the micro has minimum setup and hold time requirements.
Now look at what the microcontroller says the minimum guaranteed setup and hold times are relative to whatever clock edge it produces. Hopefully there is both more setup and more hold time that what the memory chip requires. If not, then it gets tricky because the clock needs to be skewed relative to the data.
Even more hopefully, the total setup+hold time out of the micro exceeds the minimum setup+hold required by the memory chip. If not, then the two can't be connected directly no matter how the clock is skewed relative to the data. You will need some external flip-flops or the like. That gets messy. Normally you'd use a memory chip that is compatible with the particular micro. Let's proceed assuming that is the case and the two can be connected directly.
Let's also assume that setup and hold time out of the micro (and the other direction for reading) both exceed the minimum requirement of the memory. That means you can directly connect the two, assuming a perfect connection. You also need to look at how much extra setup and hold time there is. That tells you how much skew you can tolerate between the clock and any data line.
No connection is perfect. When you're looking at individual nanoseconds, then every PCB trace is a delay line. The speed of light in vacuum is 300 mm/ns, or 11.8 inches/ns. That's a "long" distance for a PCB trace, especially when you've carefully placed the micro and memory next to each other. However, signals on PCB traces propagate slower than the speed of light. The exact speed depends on the capacitance to the ground plane, inductance of the traces, and properties of the dielectric.
This is where you should get some data from your PCB fab house. They should be able to give you some guidance on this, particularly the distance between different layers. Most of the other parameters will be reasonably similar between boards from different vendors. An 8 mil wide trace in a "1 ounce" copper layer is going to be pretty much the same thing regardless of who makes the board. Most places will use FR-4 fiberglass, although you can't leave that to chance when you care about propagation delay at this level. The main variable will be distances between layers, which affects capacitance to the ground plane, which affects propagation speed.
While you need to have some idea how much each trace will delay, what you really try to do is to match the delay between traces. You also need a solid ground plane in the next layer under where these traces will be, otherwise the delay will be unpredictable. You have to think of these traces being transmission lines, so the ground plane is an integral part of getting the signals from one end to the other.
Some memories use differential signals. In that case the transmission line is between the two signals, not with the ground plane. In that case you have to keep the two signals next to each other to keep the impedance of the transmission line reasonably constant.
In most cases, you place the chips close to each other, then route the data and clock traces so that they all have the same length. Avoid sharp turns since those add inductance and therefore more delay than the same length of trace in a straight line.
Again, it would be good to know how much time skew you have to work with. If you can afford up to 10 ns of skew, then you place the parts close to each other and things will be fine as long as the routing isn't ridiculous. If individual nanoseconds matter, then you have to pay attention to this carefully.
Also, don't forget termination of the transmission line. With differential signalling, the chips are usually designed to assume termination at each end. With single-ended signals you have to look carefully at the drive capability to see whether the drivers can tolerate the characteristic impedance. It gets tricky.
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