Activity for DavidE
| Type | On... | Excerpt | Status | Date |
|---|---|---|---|---|
| Edit | Post #290047 | Initial revision | — | 6 months ago |
| Question | — |
IEPE Sensor Internal Circuit Based on reading the All About Circuits article on IEPE sensors there are two general types of circuits integrated into this class of sensors: voltage amplifier and charge amplifier. This question regards a two wire interface in which the power unit supplies a current limited nominal voltage of typi... (more) |
— | 6 months ago |
| Edit | Post #288190 | Initial revision | — | 11 months ago |
| Question | — |
High Speed Digital Communication Bus Probing For high-speed digital communication busses, what attributes do you generally advise to add to a PCB to help with validating the communication bus as well as troubleshooting the design? In particular, I'm interested in adding features to a PCB with a parallel bus for SDR SDRAM with a clock of 167MHz... (more) |
— | 11 months ago |
| Edit | Post #288164 |
Post edited: |
— | 11 months ago |
| Edit | Post #288164 | Initial revision | — | 11 months ago |
| Question | — |
SDR SDRAM PCB Timing Budget I am working on routing a microprocessor to two identical single data rate (SDR) SDRAM chips that are PC166 compliant, particularly Alliance AS4C16M16SB-6TIN25June2021Rev2.0.pdf). The 16 bit SDRAM chips are combined to form a 32 bit word. The microprocessor is of the NXP i.MX RT1170 family and has ... (more) |
— | 11 months ago |
| Edit | Post #285375 | Initial revision | — | over 2 years ago |
| Question | — |
PCB Copper Layer Spacing & Voltage Rating One standard used for spacing conductors based on voltage is the IPC-2221. This standard differentiates spacing requirements for inner and outer conductors. Does the IPC minimum separation between conductors on an inner copper layer apply to the minimum dielectric thickness between copper layers? ... (more) |
— | over 2 years ago |
| Comment | Post #285367 |
Olin thanks for the response.
When you design a PCB for CAN or Ethernet, do you design the differential pair as loosely coupled or tightly coupled, or have you done both ways? What drives your choice?
Are there any differential signal types that you have found, or have heard of, the need to ... (more) |
— | over 2 years ago |
| Edit | Post #285361 | Initial revision | — | over 2 years ago |
| Question | — |
Design considerations for a differential pair Differential pairs, such as for ethernet or a CAN bus, can be designed to be loosely coupled or tightly coupled. For a loosely coupled differential pair, the odd-mode and even-mode impedances are roughly equivalent to the single-ended impedance (impedance of one conductor relative to the common, wit... (more) |
— | over 2 years ago |
| Comment | Post #281353 |
Olin, I have a follow question. For the microcontrollers that I see require the center tap on the transformer be tied to VDD, the Tx+ and Tx- pins are each pulled up to VDD with a 50 ohm resistor. Is the 50 ohms to match any signals reflected from the load by looking like a 100ohm differential sour... (more) |
— | about 3 years ago |
| Comment | Post #281353 |
Thanks for the extra information on the center tap. I have noticed that microcontrollers with the center tap requirement for their PHY use a pin called Rbias that needs a resistor to the return. Is rbias used for precisely setting the current sunk by Q1 and Q2 in your schematic? This current sink ma... (more) |
— | about 3 years ago |
| Comment | Post #280733 |
I like how Andy’s answer also considers the impact of the probe on the system. (more) |
— | about 3 years ago |
| Comment | Post #280714 |
Great answer by Olin. I think the answer does raise the question, why is the oscilloscope chassis and probe common being tied to earth ground if the earth ground is not benefiting the measurement? I think the answer is that the earth ground is there for electrical shock safety (same reason we elect... (more) |
— | about 3 years ago |
| Comment | Post #281353 |
Hi Olin. Thanks for the response. Would you elaborate on how the center tap tied to VDD reduces the driver complexity for a single supply system? I’m having difficulty understanding how the center tap allows for the use of low side drivers. (more) |
— | about 3 years ago |
| Edit | Post #281352 | Initial revision | — | about 3 years ago |
| Question | — |
How could you model a 10M/100M Ethernet PHY architecture? Application notes for microcontrollers or other ICs that have an internal 10M/100M ethernet PHY module differ in their requirements for the external interface components. It seems that the PHY design differs enough between devices such that the external component architecture needs to depend on whic... (more) |
— | about 3 years ago |