Activity for DSI
| Type | On... | Excerpt | Status | Date |
|---|---|---|---|---|
| Comment | Post #290284 |
Could this be an effect of the capacitor's dielectric absorption? (more) |
— | 5 months ago |
| Comment | Post #285458 |
Thank you for the detailed write-up of you approach to the design problem. I appreciate the step-by-step walk-though. (more) |
— | over 2 years ago |
| Comment | Post #285392 |
Thank you for the great write-up. The new diagrams you have added after Olin Lathrop's comment are much more clear and well drawn. (more) |
— | over 2 years ago |
| Comment | Post #285349 |
Tombstoning can still occur with a filled via, as it has to do with one SMD pad having a higher thermal mass due to the presence of the via. (more) |
— | over 2 years ago |
| Comment | Post #282575 |
Thank you for answering the initial question and for the follow up! I really appreciate you taking the time to share your knowledge and experience. (more) |
— | almost 3 years ago |
| Comment | Post #282575 |
Could I use solid state relays or would that mean having to address the same range of issues that using MOSFETs would necessitate? (more) |
— | almost 3 years ago |
| Comment | Post #282572 |
That is correct, the power electronics circuit has been redesigned to use 4x the power. (more) |
— | almost 3 years ago |