Comments on Laying out Switching Loops on PCB for Minimum Loop Area and Parasitic Inductance
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Laying out Switching Loops on PCB for Minimum Loop Area and Parasitic Inductance
Important: I know nothing about how to design a PCB or any of the jargon related to PCB designing
I am following a tutorial titled Switching Loop Layout by Prof. Alex Hanson for Texas Instruments to design my PCB.
At 7 minutes and 58 seconds Prof. Hanson mentions the impact of loop-area and loop-depth on parasitic inductance offered by a loop.
Screenshot 1
Referring to the drawing enclosed in the green box of screenshot 1:
Area enclosed by the loop = A (the blue hatched section) Depth of the loop = d (thickness of the copper) Then, at 9 minutes and 8 seconds the Prof. mentions another loop formed by folding a copper strip.
Screenshot 2
Looking at the copper strip enclosed in the green box in screenshot 2:
Area of the loop = A (area enclosed by the copper strips, in blue) Depth of the loop = d (width of the copper strip) Going by this logic he analyses three loops (one planar loop and two vertical loops).
Screenshot 3
Later in the tutorial he explains:
Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly $\frac{1}{4}$ of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below).
Screenshot 4
Screenshot 5
I do not doubt the knowledge of the speaker, however, could it be possible that he jumbled his words and instead of saying vertical loop 1 is better than vertical loop 2, he spoke the opposite? Out of the two vertical loops which will yield a smaller parasitic inductance?
I seek the opinion of the experts.
PS: He has taken the example of solenoids in a crude manner to explain the concept in a general manner. Please do not be harsh about that part.
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| User | Comment | Date |
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| ankit.kumar | (no comment) | Mar 4, 2026 at 12:24 |
Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below).
The above appears to be where you are introducing much confusion. For a start, the depth of the planar loop being smaller means less parasitic inductance yet, you appear to be saying it would produce the highest parasitic inductance. This is wrong.
Then you assert that vertical loop 1 (based on a two-layer PCB) would have less inductance. This is also wrong.
Then you say that vertical loop 2 has a depth of 14 times vertical loop 1's depth and clearly this is nonsensical. I think you meant to say 1/4 rather than 14 of course.
The bottom line is that a loop that has a smaller aperture area will have less parasitic inductance compared to one with a bigger aperture. And, the loop with the larger conductor "width" will also have less inductance.
By "width" I'm referring to the width of the PCB trace. What you refer to as depth appears to be at odds with conventional wisdom as portrayed in your second image entitled "screenshot 2". Please stick to conventions.
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