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Comments on Using FET based followers and design rules

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Using FET based followers and design rules

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Usually, voltage followers are built with bipolar transistors (or with opamps if better precision is needed). In this case, the simple rule says that the transistor emitter "follows" the input voltage one diode drop below, a somewhat approximate but understandable term.

bip-follower

It is perhaps less usual to see field effect based followers, and I'm particularly interested in jfets and mosfets.

mos-follower

From my readings about this topic, it is still unclear to me how to determine the voltage drop introduced by these transistors (parallel to the diode drop for the bipolar transistor follower).

Also, if there is a way to control this drop (without using an opamp), what are the design rules, or perhaps the rules of thumbs ?

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General comments (4 comments)
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"Also, if there is a way to control this drop (without using an oamp), what are the design rules, or perhaps the rules of thumbs ?"

"I reformulate this question:do you see any reason to use a FET follower?"

(1) As outlined by Olin Lathrop, the voltage drop (that means: The potential difference betwqeen G and S) depends, of course, on the Id=f(Vgs) relation and is less predictable if compared with bipolar transistors. More than that, I think this question concerns the DC voltage properties only.

(2) As far as the second quoted question is concerned, I think we have to consider small signals (if this stage is used as a buffer). And in this respect, the transconductance of the device matters primarily. Look at the gain formula for a CS stage:

A=gmRs/(1+gmRs)= Rs/[(1/gm)+Rs]

As we can see, for Rs>>1/gm the gain approaches unity. Of course, the exactness of the buffer function requires a transconductance as large as possible. And we know that, generally, the BJT can provide a larger transconductance. Hence, as very often in electronics, we have to find a trade-off between exactness of the follower (app. unity gain) and an input resistance (as large as possible).

But the (fixed) DC drop between G and S plays not a major role in many buffer applications.

EDIT: In the following SPICE-plot two transistors (BC107 and IRFAC30) are used as an emitter resp. source follower. Supply voltage 9V and a 5k resistor in the emitter resp. source path. The Mosfet type were selected (pos. gate voltage) to enable comparison with the BJT in a common graph.

  • Top line: Vin (DC) from 0 to 7 Volts.
  • Bottom line: Source voltage (constant offset of app.3.8V)
  • Mid line: Emitter voltage (offset app. 0.65V).

As we can see - in both cases: Output follows input with very good linearity (due to heavy feedback)

Image alt text

The jpg file has been added....hopefully

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General comments (4 comments)
General comments
coquelicot‭ wrote almost 4 years ago · edited almost 4 years ago

+1 for having pointing out that FET followers can be used advantageously to buffer small signals, where usually, only the AC part matters. They provide a nearly infinite input impedance to the signal, and the output can be passed through a cap. Good catch!

N.B: To present nicely math formulas, enclose them inside dollar signs and use Latex typesetting style.

Circuit fantasist‭ wrote almost 4 years ago

Exactly... the DC mode is interesting here since the transistor transfer curve is nonlinear.

LvW‭ wrote almost 4 years ago · edited almost 4 years ago

......but it is linearized due to negative feedback effects if the transistors are used as followers See my update (EDIT) in my detailed answer.

Circuit fantasist‭ wrote almost 4 years ago · edited almost 4 years ago

@LvW, I am trying to explain your simulation results through my graphics... but there is something that bothers me. According to my graphs, such good linearity could only be obtained if the resistor would be dynamic ("current sink") because its curve then would be horizontal. How can you explain this discrepancy?