Q&A

# Using FET based followers and design rules

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Usually, voltage followers are built with bipolar transistors (or with opamps if better precision is needed). In this case, the simple rule says that the transistor emitter "follows" the input voltage one diode drop below, a somewhat approximate but understandable term.

It is perhaps less usual to see field effect based followers, and I'm particularly interested in jfets and mosfets.

From my readings about this topic, it is still unclear to me how to determine the voltage drop introduced by these transistors (parallel to the diode drop for the bipolar transistor follower).

Also, if there is a way to control this drop (without using an opamp), what are the design rules, or perhaps the rules of thumbs ?

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Good question... I have also asked myself this question... and I must admit I do not have a convincing answer. Maybe we should take a look at H&H and Student manual for H&H... Circuit fantasist‭ 5 months ago

(A suggested edit failed with "500 server error. It was attempted more than once.) Peter Mortensen‭ 5 months ago

The title is partly incomprehensible. Is a word missing? Do you mean "Use a design rule for JFET and MOSFET followers" (one word deletion and two word additions)? Or "Use and design rules for JFET and MOSFET followers"? (one word addition. Is somewhat awkward)? Or "Use design rules for JFET and MOSFET followers"? (one word deletion and two word additions)? Or something else? Peter Mortensen‭ 5 months ago

You are right, I'll fix that. coquelicot‭ 5 months ago

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"Also, if there is a way to control this drop (without using an oamp), what are the design rules, or perhaps the rules of thumbs ?"

"I reformulate this question:do you see any reason to use a FET follower?"

(1) As outlined by Olin Lathrop, the voltage drop (that means: The potential difference betwqeen G and S) depends, of course, on the Id=f(Vgs) relation and is less predictable if compared with bipolar transistors. More than that, I think this question concerns the DC voltage properties only.

(2) As far as the second quoted question is concerned, I think we have to consider small signals (if this stage is used as a buffer). And in this respect, the transconductance of the device matters primarily. Look at the gain formula for a CS stage:

A=gmRs/(1+gmRs)= Rs/[(1/gm)+Rs]

As we can see, for Rs>>1/gm the gain approaches unity. Of course, the exactness of the buffer function requires a transconductance as large as possible. And we know that, generally, the BJT can provide a larger transconductance. Hence, as very often in electronics, we have to find a trade-off between exactness of the follower (app. unity gain) and an input resistance (as large as possible).

But the (fixed) DC drop between G and S plays not a major role in many buffer applications.

EDIT: In the following SPICE-plot two transistors (BC107 and IRFAC30) are used as an emitter resp. source follower. Supply voltage 9V and a 5k resistor in the emitter resp. source path. The Mosfet type were selected (pos. gate voltage) to enable comparison with the BJT in a common graph.

• Top line: Vin (DC) from 0 to 7 Volts.
• Bottom line: Source voltage (constant offset of app.3.8V)
• Mid line: Emitter voltage (offset app. 0.65V).

As we can see - in both cases: Output follows input with very good linearity (due to heavy feedback)

The jpg file has been added....hopefully

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+1 for having pointing out that FET followers can be used advantageously to buffer small signals, where usually, only the AC part matters. They provide a nearly infinite input impedance to the signal, and the output can be passed through a cap. Good catch! N.B: To present nicely math formulas, enclose them inside dollar signs and use Latex typesetting style. coquelicot‭ 5 months ago

Exactly... the DC mode is interesting here since the transistor transfer curve is nonlinear. Circuit fantasist‭ 5 months ago

......but it is linearized due to negative feedback effects if the transistors are used as followers See my update (EDIT) in my detailed answer. LvW‭ 5 months ago

@LvW, I am trying to explain your simulation results through my graphics... but there is something that bothers me. According to my graphs, such good linearity could only be obtained if the resistor would be dynamic ("current sink") because its curve then would be horizontal. How can you explain this discrepancy? Circuit fantasist‭ 5 months ago

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FET source-followers are generally less predictable than BJT (bipolar junction transistor, like NPN or PNP) emitter-followers.

An emitter follower output is one diode drop below the input. The voltage across a diode varies little as a function of the current, so this offset remains fairly constant. The absolute voltage across this diode is also reasonably predictable.

The input to output drop of a FET source-follower is whatever gate voltage is required to pass the source current. The absolute value of that voltage is less well specified than the drop on a silicon diode.

Take a look at gate threshold voltage specifications for some common FETs. I just looked up the IRLML2502 as an example of a low voltage FET meant to be driven with logic level gate voltages. Even this FET is specified for a gate threshold voltage anywhere from 600 mV to 1.2 V, and that's just at 250 µA.

Take a look at the typical characteristics of what gate voltage is required to sustain what collector current:

First, notice how little this graph really tells you. It only shows currents from around 15 mA to a bit over 30 mA. It's not of much help if your current is only, 2 mA, for example.

Second, notice the rather large change in gate voltage to get different channel currents. Even at the single fixed temperature of 25 °C, it takes 2.5 V to get 20 mA, and over 3 V to get 30 mA. At 150 °C it takes over 3.4 V to get the same 20 mA.

Another characteristic to consider is the how much D-S voltage is needed before it no longer matters much:

It takes about 1 V or so at 15 mA, and over 2 V at higher currents. Contrast that to a BJT where this is well under 1 V except at quite high currents for the device.

So even for this one example low voltage FET, the G-S voltage varies much more than the B-E voltage of a BJT, and more D-S voltage is required before that stops being much of a dependency. These characteristics are even worse for higher voltage FETs which are usually intended to operate with a 10 V or so gate range.

All around, This means that the G-S voltage of a FET is less predictable to start with, and will vary more, than the B-E voltage of a BJT in similar conditions. Since all the G-S or B-E voltage variations show up directly on the output of follower circuits, FETs simply don't make as good followers as BJTs do.

do you see any reason to use a FET follower?

A FET follower can be used when the larger and less certain delta from input to output voltage is acceptable.

One advantage of a FET follower is very high input impedance, and that is independent of the current being delivered to the load. That means FET followers have much higher current gain than BJT followers.

But a current gain of (practically) zero at DC (only the leakage current (on the order of 1 pA) is flowing(?)?

The current gain is the output current divided by the input current. For a BJT follower, that is Iemitter/Ibase = β+1. For a FET follower, it is Isource/Igate. Since the gate current is only leakage, the current gain of a FET follower is very high for anything more than tiny output currents.

As was pointed out in a comment, "current gain" doesn't really make sense when the output current isn't some reasonable function of the input current. That is not the case with a FET follower. I was only trying to point out that the input of a FET follower has high impedance. Essentially no current (just leakage) is drawn from the source signal, although that signal controls substantial output current. This is in contrast to a BJT follower where the output current is reasonably proportional to the input current, and the ratio is gain+1 of the transistor.

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@Olin Lathrop. Thank you for your answer. So, should I understand it as : No use of FET followers in electrical engineering? Edit: I reformulate this question: do you see any reason to use a FET follower ? coquelicot‭ 5 months ago

Re "FET followers have much higher current gain": But a current gain of (practically) zero at DC (only the leakage current (on the order of 1 pA) is flowing(?)? The first graph was for a 20 µsec pulse. Peter Mortensen‭ 5 months ago

(OK, for the value of the leakage current: It depends.) Peter Mortensen‭ 5 months ago

And yet it is strange to talk about current gain here... Leaks are unpredictable. Circuit fantasist‭ 5 months ago

Yes - very strange. It can lead to the (false) assumption that the output current Id would be an amplified version of the (parasitic) input current. LvW‭ 5 months ago

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Allow me to address the MOSFET only as a source follower.

• this has very unpredictable linear use without voltage = current feedback as the RdsOn at threshold has a wide tolerance.(>20%) (Many wider than the next example). However it is extremely popular in dual N ch. designs for a Half Bridge switching PWM design. The Source Follower is the high side switch and the Common Source is the Low Side PWM switch.

I picked a 1 mohm Nch FET 40V 200A , IAUA200N04S5N010 from Infineon.

Vgs(th)@100uA = 2.8V +/- 0.6V ( Thus Rth = 2.8V/100uA = 28kohm

Then RdsOn= 1.3 mOhm (max) @Vgs=7V and 1.0mOhm (max) @ Vgs=10V

Since your Vg (in) = Vgs + Vs (out) and the output switches towards Vdd Vg must be at least 7V greater than Vdd. This is no problem if Vdd is at least 10V with a diode- cap Boost “voltage doubler” clamped to produce a voltage above Vdd.

Usually in a dual Nch. half bridge you generate this Vgs greater than the Vdd using the low side for PWM so a diode cap can create the well known “boost” above Vdd for the high side source follower.

The other way to remember how this works is that to get a close to spec RdsOn there is a convenient ratio of

## Vgs/Vgs(th)=~7V/2.8V=2.5 ratio minimum

and 3 preferred to meet RdsOn spec. This ratio is universal for Vgsth in the 2V range but reduces slightly for sub threshold devices ~ 1V range.

For RF linear design there are many rules which are TL;DR for most.

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and I'm particularly interested in jfets and mosfets.

If you decide to go down the FET route the dilemma between J and MOS gets down to home much you are willing to pay in order to have less noise in the next stage.

MOSFET's have the conducting channel under the gate oxide and like nothing in this world the channel is not 100% "clean" - it has defects. These defects reduce the mobility of electrons which flow through it which as a result has higher 1/f noise. JFET's add a depletion layer between the gate and the conducting layer so they have less 1/f noise. They are quite often used as preamplifiers in the audio industry.

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... it is still unclear to me how to determine the voltage drop introduced by these transistors...

Very interesting question... I have asked myself many times in the past... and I have not been able to answer it... but now I think I have already succeeded... Maybe Codidact acts as a kind of "catalyst" for my creative thinking:) In addition, the principle of negative feedback and Mr Hayes with his Student Manual for the Art of Electronics (my favorite book from the past) helped me realize the idea.

"Negative feedback" here means that the transistor (JFET) passes its drain current through the source resistor thus trying to increase the voltage drop across it. But this voltage is applied to the gate-source junction so that to decrease the drain current. As a result, equilibrium is achieved. And the OP's question is, "How much is VGS?" I would ask the same about ID. So we need to know both...

It is obvious the question is about a large DC input signal varying between the supply rails. The transfer characteristic Id = f(Vgs) is nonlinear and the transconductance gm cannot be used. Then Mr Hayes suggested solving the circuit graphically. I have extracted below three consecutive steps from his explanations. Let's consider them.

1. Simplest JFET current source. Compared with BJT, JFET is a weird device because it has an NP junction but it is backward biased... and the transistor is fully on when the voltage across this junction is zero. To make it zero, we can simply join the gate and source (Fig. 1 left), thus obtaining the simplest possible JFET current source. This connection is very useful in this application since the 3-terminal transistor is made act as a 2-terminal current-stabilizing "diode".

Fig. 1. To make VGS - 0, we can simply join the gate and source.

The intersection point between two curves (the JFET's IV curve and the ordinate axis) gives the graphical solution (Fig. 1 right). There is no negative feedback in this arrangement.

2. Self-biased JFET current source. To set the desired current, we can insert a source resistor Rs (between the gate and source) - Fig. 2 left. The negative feedback comes into picture (as I have explained it above) and the equilibrium is reached. It is interesting to see the graphical solution for this case - Fig. 2 right.

Fig. 2. Self-biased JFET current source.

I had a problem understanding this graphical interpretation because I had the usual idea of this visualization technique - the curves of two elements (for example a diode and a resistor) overlap in the same coordinate system and their intersection (operating) point gives the solution. But they are "ordinary" elements with two terminals between which the current passes and voltage drop appears.

The problem here is that the one of them is a "trans element" since the voltage appears across one place but the current flows through other place. But the trick here is that, for the purposes of this graphical presentation, it is thought of as a "composed" 2-terminal element with its nonlinear IV curve. It is as if both the current and the voltage are its... but that is just an illusion.

The "trans element" can be considered as a virtual element whose voltage is the original VGS but the current Id is artificially created according to the trans curve.

Note the resistor is represented by a reversed IV curve (line). The intersection point between it and the JFET transfer curve gives an answer to the OP's question.

3. Self-biased JFET source follower. The situations above were static. Let's now include an input voltage. We can do it in various ways - as in Fig. 3 through a capacitor (small AC)... or just connecting the input voltage source between the gate and ground (in series to the gate-source junction). Thus its voltage will be added/subtracted to/from the voltage drop across the resistor.

Fig. 3. Self-biased JFET source follower.

It is interesting to imagine what the graphical interpretation will be (Mr. Hayes has not provided us with an illustration; so we will have to imagine it ourselves). I think the JFET IV curve will move horizontally (translate)... and the intersection point will move along the R IV curve (the "load line"). It would be good to draw it... OK, let's do it.

Fig. 4. JFET source follower with Vin (quickly sketched)

But why not use the same technique to show the operation of the classic emitter follower?

Fig. 5. Emitter follower with Vin (quickly sketched)

Note the transistor is represented by a reversed IV transfer curve. Here the "trans element" can be considered as a virtual element whose original current IB is modified by adding beta x IB current to it.

And here is another challenge for your imagination - the same two pictures but with additionally shown "dynamic resistance" RDS and RCE (thin lines starting from the beginning of each IV curve and crossing the operating point).

Fig. 6. JFET source follower with dynamic resistance RDS visualized

Fig. 7. Emitter follower with dynamic resistance RCE visualized

If necessary, I will add more explanations to the last two figures to clarify how the non-linear transfer curve is obtained by the concept of "dynamic resistance"...

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