Comments on What is the role of master clock speed on DAC
Parent
What is the role of master clock speed on DAC
In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin Lathrop): 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
Question 4: Also the datasheet mentioned 1x/2x/4x/8x interpolatino is availible, but there isn't way to setting it, does it relate to MCK?How?
Post
The following users marked this post as Works for me:
| User | Comment | Date |
|---|---|---|
| mohammadsdtmnd | (no comment) | Feb 6, 2024 at 20:08 |
| mohammadsdtmnd | (no comment) | Feb 6, 2024 at 20:08 |
| mohammadsdtmnd | (no comment) | Feb 6, 2024 at 20:08 |
| mohammadsdtmnd | (no comment) | Feb 6, 2024 at 20:08 |
In protocol I2S we have 4 signal: 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
Not really. IIS really only has 3 signals: bit data, bit clock, and left/right indication. Take a look at the actual IIS protocol from NXP.
Some implementations do use a "master clock". This is sometimes the l/r signal divided by 256 or somesuch. If used, it tends to be for higher level synchronization.
It looks like your D/A expects plain IIS, and doesn't connect to any master clock if there is one.
0 comment threads