When and where to use vias in an IC design layout
I am learning IC design layouts using Cadence Virtuoso and now I got stuck with the concept of using vias. The question is when and where to use it? I am attaching the schematic of my inverter tutorial 
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Vias are used to move up in metal layers. The contacts of the transistors can be directly connected with metal 1, but if you want to use higher metal levels, you move up to them with vias.
For example, if you use M1 (metal 1) and you need to cross another M1 trace that does not belong to your node, then you need to avoid it. You could use a via to M2 to avoid this trace.
Another very good reason to move up in metal layers is that, at least in deep submicron technologies, the higher metal layers have less resistivity than the lower ones.
For instance, I have experience with a particular technology where a few tens of micrometers can easily amount to a few hundreds of ohms, while higher metals can be only few ohms.
This means that metal layers also have their applications within a design. For an analog design, lower metal layers can be used to wire up static logic circuits (such as enable bits). In those cases, a few 100 ohms of wire typically doesn't matter, speed or a few 10s of mV are not important. On the other hand, higher metal layers can be used to wire up the amplifier itself, as you certainly don't want to be inserting parasitic series resistors on your nodes. Otherwise, you might degrade your amplifier's performance in a post-layout simulation.
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