Activity for Olin Lathrop
| Type | On... | Excerpt | Status | Date |
|---|---|---|---|---|
| Edit | Post #293911 | Initial revision | — | 3 days ago |
| Answer | — |
A: Potentiostat Clarification needed What the top part of the circuit really does is drive the counter electrode to whatever it takes to null out the voltage on the reference electrode. The null comes from what the positive input of IC2 is set at, which is ground in this case. I'm not familiar with these types of sensors, but it loo... (more) |
— | 3 days ago |
| Edit | Post #293897 |
Post edited: |
— | 4 days ago |
| Edit | Post #293897 |
Post edited: |
— | 5 days ago |
| Edit | Post #293897 | Initial revision | — | 5 days ago |
| Answer | — |
A: Should we have a sub-forum for less structured, forum-style discussions? Back and forth discussion is not suited to the Q&A format that this web site is set up for. As far as I know, the Codidact software is not capable of a category that supports threaded discussions anyway. Discussions also tend to have low signal to noise ratio. The high density of quality content i... (more) |
— | 5 days ago |
| Edit | Post #293879 |
Post edited: |
— | 9 days ago |
| Edit | Post #293879 | Initial revision | — | 10 days ago |
| Answer | — |
A: Speaker receives interference WiFi or cell phone signals are way too fast for you to hear individual dits and dahs, and they don't use that kind of encoding anyway. What you are hearing is the carrier from a local ham radio operator sending morse code getting unintentionally detected by the electronics in your sound system. T... (more) |
— | 10 days ago |
| Edit | Post #293877 | Initial revision | — | 10 days ago |
| Answer | — |
A: Cable Capacitance and Barrier/Cable/Sensor Circuit Geometry Evaluation for Intrinsically Safe Circuits why it is acceptable to reduce what appears to be a fairly complex capacitance “network” down to a single value for use in the “allowable capacitance” calculation for a barrier? Because you only care about the worst case when it comes to Intrinsic Safety. In this usage, there is an upper limit on... (more) |
— | 10 days ago |
| Edit | Post #293854 |
Post edited: It's obviously a question |
— | 14 days ago |
| Edit | Post #293856 | Initial revision | — | 14 days ago |
| Answer | — |
A: Cable Capacitance In Intrinsically Safe Systems The reason for the maximum capacitance spec is to limit stored energy that could cause a spark when that energy is released all at once. There are tables and equations that show how much capacitance is allowed for any given voltage. You should therefore use your CS value. According to your descr... (more) |
— | 14 days ago |
| Edit | Post #293779 |
Post edited: Fixed typo |
— | 23 days ago |
| Edit | Post #293779 | Initial revision | — | 25 days ago |
| Answer | — |
A: Matching network considerations for STM32WB55CEU6 I see that in evaluation design it is mentioned component values will be updated after evaluation, so is it the case that these values are more or less arbitrary and tuned with a VNA during proto testing? That was my first thought when I read that disclaimer. Your original analysis suggested th... (more) |
— | 25 days ago |
| Edit | Post #293708 |
Post edited: |
— | about 1 month ago |
| Edit | Post #293708 | Initial revision | — | about 1 month ago |
| Answer | — |
A: Shared ground path vs shared supply path Understand the physics, and then you don't need these silly and often misleading "guidelines". Such myths may have started with a kernel of truth, but the limitations and conditions under which they apply are usually forgotten to the point that the result is too often wrong. Mostly, they are crutch... (more) |
— | about 1 month ago |
| Edit | Post #293668 |
Post edited: |
— | about 1 month ago |
| Edit | Post #293668 |
Post edited: |
— | about 1 month ago |
| Edit | Post #293668 |
Post edited: |
— | about 1 month ago |
| Edit | Post #293668 | Initial revision | — | about 1 month ago |
| Answer | — |
A: Using split CT termination for better THD performance Your question is answered in the very next sentence in the datasheet after the one you quoted: This split-burden resistor configuration ensures that the waveforms fed to the positive and negative terminals of the ADC are 180 degrees out-of-phase with each other, which provides the best THD result... (more) |
— | about 1 month ago |
| Edit | Post #293482 | Initial revision | — | 2 months ago |
| Answer | — |
A: Changing PCB trace width once signal-to-noise ratio is high Trace width is a silly thing to worry about at such low currents and high impedances. You've got 1 MΩ resistances in the signal path, and the opamp input is presumably much higher impedance than that. You didn't say what the upper limit of your signal frequency is, but lets say 1 kHz since ... (more) |
— | 2 months ago |
| Edit | Post #293403 | Initial revision | — | 3 months ago |
| Answer | — |
A: Tesatronic TTD20 DGND AGND unconnected I'm not familiar with this device, but it is possible that different variants were made or were possible with the same PCB. Consider the documentation you have as general guidance, not necessarily exact. I've seen this a lot with old devices like that. (New devices solve this problem by not provid... (more) |
— | 3 months ago |
| Comment | Post #293398 |
This site is not for getting others to do your homework for you. We might be able to guide you to a solution when you get stuck, but we're not just going to hand you one.
Try asking specific questions, explain what you don't understand, and what you did to try to solve the problem. (more) |
— | 3 months ago |
| Edit | Post #293398 | Question closed | — | 3 months ago |
| Edit | Post #293382 | Initial revision | — | 3 months ago |
| Answer | — |
A: Power polygon and matching ground For power polygon that primarily carry DC, how critical is it that it is located above a ground plane? Practically not at all. Power planes are overrated. Think about what problem you are really trying to solve. If you have high power currents, then you need to use wide and/or thick traces. ... (more) |
— | 3 months ago |
| Edit | Post #293381 | Initial revision | — | 3 months ago |
| Answer | — |
A: Signals and plane on the same layer When placing traces on this ground plane, is it better to Keep them as tightly packed as possible, grouping them into a concentrated "island" within the ground pour (Image 1)? Space them out slightly, allowing the ground pour to flow between them, thereby increasing the overall ground area surr... (more) |
— | 3 months ago |
| Edit | Post #293361 |
Post edited: |
— | 3 months ago |
| Edit | Post #293380 | Initial revision | — | 3 months ago |
| Answer | — |
A: Does My Circuit Contain High-Speed Signals? No, none of your signals sound like "high speed". However, that doesn't mean you should ignore high frequency noise issues. If you can dedicate one layer to be mostly a ground plane, that would be good. If this is a high volume product optimized for low cost, then you get creative with only two ... (more) |
— | 3 months ago |
| Edit | Post #293375 |
Post edited: Enough with the annoying fluff! This is now the second time I had to edit it out. Read the rules already! |
— | 3 months ago |
| Edit | Post #293379 | Initial revision | — | 3 months ago |
| Answer | — |
A: Thick trace or a Polygon? Not much. If the wide power trace is good enough to handle the current, then it's, well, good enough. If you really don't have anything else to do with the copper space, then you might as well make the power trace wider, but there is a usefulness limit. (more) |
— | 3 months ago |
| Edit | Post #293359 |
Post edited: Removed content-free fluff. |
— | 3 months ago |
| Edit | Post #293361 | Initial revision | — | 3 months ago |
| Answer | — |
A: Thermal Relief – Yes or No? The main point is that you need thermal symmetry between the two pads of a small package. You want the solder paste to melt at the same time between the two pads. Molten solder has significantly higher surface tension than solder paste. When the solder melts, the surface tension will try to "lev... (more) |
— | 3 months ago |
| Edit | Post #293356 |
Post edited: |
— | 3 months ago |
| Edit | Post #293356 | Initial revision | — | 3 months ago |
| Answer | — |
A: Dual ratiometric power scaler design review and issues Partial answer awaiting more specs Your question can't really be answered until we know how accurate the resulting solenoid drive levels need to be relative to the 0-10 V input signals, and how fast the system must respond. However, here are a few observations in the mean time: Use a microcont... (more) |
— | 3 months ago |
| Comment | Post #293355 |
What accuracy? What frequency response? (more) |
— | 3 months ago |
| Edit | Post #293350 | Initial revision | — | 3 months ago |
| Answer | — |
A: Solder mask bridge issue Talk to your board house. 4 mil slop for the soldermask around pads is excessive. Leaving 4 mils is fine for larger parts, but as you say, it doesn't work for fine pitch. The main reason for making the soldermask hole larger than the pad is to allow some room for mis-registration between the cop... (more) |
— | 3 months ago |