Activity for 2kindâ€
| Type | On... | Excerpt | Status | Date |
|---|---|---|---|---|
| Comment | Post #279732 |
Thanks Olin! So for floating loads, low side switching + galvanically isolate communication interface could potentially be used instead of a high side switch? (more) |
— | over 3 years ago |
| Comment | Post #279728 |
@AndyAka The reason behind having two series MOSFETs is to prevent charging of the battery through the body diode when the FET is on. (more) |
— | over 3 years ago |
| Edit | Post #279728 |
Post edited: Added pictures and changed the questions |
— | over 3 years ago |
| Edit | Post #279728 | Initial revision | — | over 3 years ago |
| Question | — |
High Power Switch - High Side vs. Low Side Switching Imagine a battery pack with <=60VDC of maximum voltage and a load of up to 10kW of power(the PMSM inverter with the input capacitance of up to 1mF). The load is not always known - could be 100uF-1000uF input capacitance while the currents usually range from 20A up until 150A. The load is switched on/... (more) |
— | over 3 years ago |
| Edit | Post #279033 | Initial revision | — | over 3 years ago |
| Answer | — |
A: Using FET based followers and design rules In addition to Olin's answer: > and I'm particularly interested in jfets and mosfets. If you decide to go down the FET route the dilemma between J and MOS gets down to home much you are willing to pay in order to have less noise in the next stage. MOSFET's have the conducting channel un... (more) |
— | over 3 years ago |
| Comment | Post #279010 |
Thanks Olin! You are right, the A1A is not connected correctly.
https://www.st.com/resource/en/datasheet/tsv324a.pdf
The data about ESD is very vague - it says it could withstand 2kV using Human Body Model, but for example, doesn't have a schematic of how the opamp is realized internally like s... (more) |
— | over 3 years ago |
| Comment | Post #279005 |
Thank you @Circuit fantasist. I am okay with the leakages because the thresholds for A1B and A1C would be set up conservatively.
Do you think the TVS between opamp inputs is needed for limiting the differential signal? (more) |
— | over 3 years ago |
| Comment | Post #278989 |
Thanks Andy. I've updated the question above! (more) |
— | over 3 years ago |
| Edit | Post #278989 |
Post edited: Added part after "edit" - further explanation |
— | over 3 years ago |
| Comment | Post #278989 |
It's "the TVS diodes". There is no TVS diodes on the schematic but I would like to put them in order to make the circuit ESD immune for both differential and common mode signals. (more) |
— | over 3 years ago |
| Edit | Post #278989 | Initial revision | — | over 3 years ago |
| Question | — |
ESD Protection - Differential Amplifier Circuit under discussion More about the circuit The circuit is sensing (low side sensing for many reasons) current used to power up the lights with 28V(part of the schematics not shown here -> relay with LC filter on the output side to limit the inrush current). The nominal current flowing th... (more) |
— | over 3 years ago |
| Comment | Post #278484 |
I guess you could tweak the "secondary" of the trafo and aim for aslightly higher voltage - then you simply put linear regulator and reduce the ripple. (more) |
— | over 3 years ago |
| Edit | Post #278456 | Initial revision | — | over 3 years ago |
| Question | — |
High Speed Design - Which grounding strategy to choose? Although I have done multiple PCB designs which passed FCC and CE equivalents using the MCU's/Multiple MCU's, I have a doubt about how to approach the high speed design using FPGA SoC - main thing that bothers me is choosing the right grounding strategy. By the high-speed design I mean >2GHz memor... (more) |
— | over 3 years ago |
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