Activity for TonyStewartâ€
| Type | On... | Excerpt | Status | Date |
|---|---|---|---|---|
| Comment | Post #293514 |
Carl, None of your ideas make sense.
1. Discrete tolerances reduce your CMRR significantly.
2. You are analyzing with DC rather than AC and BW. Which spectrum do you need to block and pass? Although Galvanic skin response is DC until motion modulates it.
3. How you computed path loss from the ... (more) |
— | about 1 month ago |
| Edit | Post #293514 |
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— | 2 months ago |
| Edit | Post #293514 | Initial revision | — | 2 months ago |
| Answer | — |
A: Changing PCB trace width once signal-to-noise ratio is high None of these ideas optimize the SNR that you need. You need to design with error correction or (suppression); - 50V/m grid E-field (Right Led Drive RLD) >100 dB suppression - AM radio noise (LPF > -40dB @ 1MHz) - Galvanic skin response (motion artifacts) (firm electrode strain relief) If... (more) |
— | 2 months ago |
| Comment | Post #293360 |
Do you have any PDN ripple specs? Load Transient specs?, Step load current? (more) |
— | 3 months ago |
| Edit | Post #293463 |
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— | 3 months ago |
| Edit | Post #293463 |
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— | 3 months ago |
| Edit | Post #293463 | Initial revision | — | 3 months ago |
| Answer | — |
A: Tesatronic TTD20 DGND AGND unconnected I see Imagealttext and from the photo left to right , the 3 regulators are ; +15, -15 , + 5.0 LM324-15 LM320-15 LM324-50 The +ve LDO's share the same heatsink with insulator + plastic screws. To sharing Dgnd noise with analog ground , you can use Dgnd from the 5V out using this pho... (more) |
— | 3 months ago |
| Comment | Post #293360 |
Your question is vague and unanswerable without knowing risetime, signal impedance, thus tolerance to crosstalk capacitance determined by coplanar trace gap. Using thin 5 thou guard tracks between high impedance signals reduces crosstalk. (more) |
— | 3 months ago |
| Comment | Post #293398 |
For your undergraduate, I would expect more challenge than a low-Fi 2 transistor per stage amplifier. Damping Factors of 1000 are achieved and you should understand why this matters in high power and high-quality sound systems. Don't ever think you can copy schematics not produced in large quantity... (more) |
— | 3 months ago |
| Edit | Post #293394 | Initial revision | — | 3 months ago |
| Answer | — |
A: Signals and plane on the same layer Based on very little information and you just starting PCB layouts, you may be overthinking this problem or rightly concerned. There are a lot of fundamentals you might already know about how to make a capacitor and inductor using just a PCB trace and ground plane. Generally, ground planes are ... (more) |
— | 3 months ago |
| Comment | Post #293363 |
What are your concerns for crosstalk or EMI and parasitic capacitance?
Do you think all this power or ground plane can hurt anything?
For example, ground/power planes are bad under inductors if lowering self-resonant frequency causes a problem . (more) |
— | 3 months ago |
| Edit | Post #293391 | Initial revision | — | 3 months ago |
| Answer | — |
A: Does My Circuit Contain High-Speed Signals? If there are high slew rate signals or high-impedance circuits, layout matters. Otherwise, it usually doesn’t. Slew Rate (SR) in the time domain translates to bandwidth in the frequency domain, so you can analyze it either way. Technically, anything between 30 MHz and 300 MHz is considered high... (more) |
— | 3 months ago |
| Comment | Post #293009 |
If the user only has a few quantized thresholds to detect then the linear effects at Vo=0 are irrelevant within any human speed. But if microsecond response times are needed special designs are required with reverse bias adequate BW, slew rate and linearity. But not for your typical application. (more) |
— | 5 months ago |
| Edit | Post #293093 | Initial revision | — | 5 months ago |
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A: Moving average that uses less memory? I would suggest finding the root cause of all the noise and eliminate as much of it at the source. Baluns, active guarding, double shielding, buffering, current source control and matched impedance T-lines are some of the methods to do that. Define your existing SNR and desired result. Then rec... (more) |
— | 5 months ago |
| Comment | Post #293082 |
For common-mode e-field, you need to consider all sources are unbalanced but fortunately low impedance. If necessary use a TIA with a current loop into a remote termination R=100.
STP wire will help lower ingress with the shield terminate at one end only to avoid unintended ground loops.
A CM ... (more) |
— | 5 months ago |
| Comment | Post #292090 |
It ought to be a continuous test for PE gnd like an RCD at these power levels for car & human safety.
Ground is just 0V in theory a local reference point regardless if it is floating like earth. (more) |
— | 9 months ago |
| Edit | Post #292192 | Initial revision | — | 9 months ago |
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A: Circuit for earth conductor presence detection Fault Codes (Page 38) Tesla gnd fault codes PE ground is mandatory to be functional and is tested. Typical standards expect < 25 Ohms for residential zones. RCD's and similar testers use as test resistor to force an unbalance current using well-balanced common mode latching relay.... (more) |
— | 9 months ago |
| Edit | Post #292188 |
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— | 9 months ago |
| Edit | Post #292188 |
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— | 9 months ago |
| Edit | Post #292188 | Initial revision | — | 9 months ago |
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A: Are LDOs more efficient than switching regulators in very low currents? One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. IC's with very low V logic-level FETs (Vt=0.65) are used in a 1.2V supply. Low noise is preferred for Vref and Va on ADCs used by some uC's. The voltage rati... (more) |
— | 9 months ago |
| Edit | Post #292187 |
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— | 9 months ago |
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— | 9 months ago |
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— | 9 months ago |
| Edit | Post #292187 |
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— | 9 months ago |
| Edit | Post #292187 |
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— | 9 months ago |
| Edit | Post #292187 | Initial revision | — | 9 months ago |
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A: Purpose of resistance between SENSE/FORCE line of power supply This looks like the block diagram was done by a technical writer, not the designer. It is someone's conceptual misunderstanding of a linear servo with feedback relays and optional FET drivers with error amplifiers (and R5) between Vo and Sense (not accurate). It has no power supply. Some old H... (more) |
— | 9 months ago |
| Edit | Post #291315 | Initial revision | — | about 1 year ago |
| Answer | — |
A: Control logic for mosfet in piezoelectric energy harvesting circuit Every real part has resistance including your piezo current source. Every switch resistance is a loss in energy (I^2 R t)=E and includes diode and transistor switches. What you need, I think, is to incorporate MPT theory into your block diagram and use a goal of matched impedances to achieve it. ... (more) |
— | about 1 year ago |
| Comment | Post #290874 |
FR-4 and soldermask will slowly absorb moisture under pressure. https://www.nextpcb.com/blog/waterproof-pcb--nextpcb (more) |
— | about 1 year ago |
| Comment | Post #290595 |
When I did Hipot testing, I modified the tester with a string of resistors to current limit and prevent destructive failures yet trigger insulation failures in the 100uA test. When I tested 5 MVA transformers to 200kV, I used an AM radio and LeCroy scope to measure partial discharge (PD) events befo... (more) |
— | over 1 year ago |
| Comment | Post #290595 |
"When should a transformer core be potted?"
>When being attacked by environmental stress from all sides.
"Should it be potted at all? "
> It is not mandatory. Consider if Dk affected the frequency applied or the thermal temperature from insulation. This may not be in your case, but just ... (more) |
— | over 1 year ago |
| Edit | Post #290722 |
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— | over 1 year ago |
| Edit | Post #290722 |
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— | over 1 year ago |
| Edit | Post #290722 |
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— | over 1 year ago |
| Edit | Post #290722 |
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— | over 1 year ago |
| Edit | Post #290722 |
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— | over 1 year ago |
| Edit | Post #290722 |
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— | over 1 year ago |
| Edit | Post #290722 | Initial revision | — | over 1 year ago |
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A: estimation of pogo pin resistance I agree with Olin that unknown contact area is the biggest variable. I think the scientific way is to test and verify each contact using a 4 pin kelvin bridge. The sum of 2 pins carrying constant current can be measured as voltage by 2 adjacent pins on pads sufficiently large. It probably wo... (more) |
— | over 1 year ago |
| Edit | Post #290720 |
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— | over 1 year ago |
| Comment | Post #290720 |
My assumptions were based on analyzing the photo of the transparent substrate that the membrane switches were bonded to without any conductive traces. Yet on the same side below them was the carbon printed traces connecting the domed membranes beneath the clear substrate. It is true that membrane sw... (more) |
— | over 1 year ago |
| Edit | Post #290720 | Initial revision | — | over 1 year ago |